The present invention relates generally to aligning patterns on substrates, and in particular, to accurate front-to-back alignment of patterns on a semiconductor wafer.
In semiconductor manufacturing, the processing steps for fabricating a semiconductor device involve exposing a substrate using a lithographic exposure system, such as exposing a semiconductor wafer coated with photosensitive material. This exposure requires aligning a reticle having a pattern of a particular device layer to an existing pattern on the substrate. After alignment, the reticle is exposed to radiation to which the photosensitive coating is sensitive, which transfers the reticle pattern onto the wafer.
Alignment marks and the alignment of subsequent lithographic patterns with respect to those marks are an important part of the semiconductor manufacturing process. Alignment of one pattern layer to previous layers is typically done with the assistance of special alignment patterns designed on a previous mask layer. When these special patterns are aligned, it is assumed that the remainder of the circuit patterns is also correctly aligned.
In some lithographic applications, the three-dimensional nature of the devices being produced requires precise alignment of the structure from the front side through the backside of the substrate. In certain cases, the substrate is processed on one side, and then flipped over and processed on the opposite side to create the desired three-dimensional structure. In such cases, the front side and backside must be properly aligned to form the patterned structure.
Conventional alignment of a pattern on the bottom surface of a wafer to a pattern on the top surface, i.e., front-to-back alignment, is typically done with either an infrared mask aligner for aligning through the substrate, or by requiring the wafer to have straight edges and using the straight edges as references for both top and bottom patterns. Other prior art methods include designing alignment markers, which are part of the metallization on the front side of the wafer, and exposing the markers by etching the wafer such that the backside pattern is directly aligned with the front side pattern using the etched alignment markers on the backside as the guide.
Backside processing of silicon wafers provides many challenges. The present invention addresses a problem in optical lithography concerning pattern alignment on the backside of wafers. Once a wafer is flipped over, alignment marks printed during topside processing are reversely aligned between different edges of the chip, as the mirror image of themselves. In this instance, the alignment marks on the reticle no longer line up with the alignment marks on the now upside-down wafer, since those on the wafer are located differently, as mirror images, whereas those on the reticle remain unchanged.
Currently, costly alignment tools are utilized to visually inspect the bottom of the wafer once the wafer is turned over (the former wafer top), for alignment marks while aligning subsequent masks to the wafer top (former wafer bottom). Another method for addressing this problem is to have the reticles aligned to the backside as mirror images of the data. Both solutions are costly and time consuming in application.
In U.S. Pat. No. 4,669,175 issued to Ray on Jun. 2, 1987, entitled “FRONT-TO-BACK ALIGNMENT PROCEDURE FOR BURRUS LED'S,” a method for accurate front-to-back alignment is taught where a metallization layer has perpendicular alignment indicia intersecting at metal contact on the front surface of the wafer. The perimeter of the wafer is etched away to reveal the alignment indicia, which are detected and visible from the backside of the wafer. The back surface contact pattern is then aligned using the newly exposed part of the top surface, i.e., the front side alignment indicia.
In Japanese Patent JP7147386A issued to Kozuka Eiji and published on Jun. 6, 1995, entitled “SEMICONDUCTOR DEVICE AND ITS MANUFACTURING METHOD AND APPARATUS USED FOR IT,” patterns for two chips, namely one chip of normal type and one chip of reverse type, are formed on the same mask blank. The same data in an integrated circuit data region formed on each semiconductor chip are shared and the direction is the mirror image for the layout; however, the chip is not flipped over for processing where the mirrored image pattern could be used for alignment purposes, nor are any alignment modifications made to the backside.
In U.S. Pat. No. 3,752,589 issued to Masaaki Kobayashi on Aug. 14, 1973, entitled “METHOD AND APPARATUS FOR POSITIONING PATTERNS OF A PHOTOGRAPHIC MASK ON THE SURFACE OF A WAFER ON THE BASIS OF BACKSIDE PATTERNS OF THE WAFER,” a method of aligning the pattern of a photo mask on one side of a wafer to the patterns placed on the underside of the wafer is taught. The alignment of the mask with respect to the wafer is achieved by optically superimposing the images present on the mask and on the underside of the wafer and adjusting the mask relative to the wafer until the relative positions of the combined images are corrected to a predefined set of conditions. This method requires two viewing apparatus: one for the mask facing the wafer and the other on the opposing side facing the underside of the wafer. Moreover, this art requires an etch from the front side rather than backside processing techniques.
Bearing in mind the problems and deficiencies of the prior art, it is therefore an object of the present invention to provide a method for pattern alignment on the backside of wafers.
It is another object of the present invention to provide a method for pattern alignment using front side alignment tools.
A further object of the present invention is to provide a method to solve the problem associated with alignment marks that are printed during topside processing and become reversely aligned between different edges of the chip on the backside.
Still other objects and advantages of the invention will in part be obvious and will in part be apparent from the specification.